ASIC design project manager

☞ QPlox engineering BVBA

Vue: 135

Jour de mise à jour: 16-11-2025

Localisation: Leuven Flemish Brabant

Catégorie: Production/Opération

Industrie:

Type d’emploi: Voltijds, Vaste Jobs

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le contenu du travail

About the company

Qplox is a fast growing company offering test and automation engineering. Headquartered in Leuven, with offices in Barcelona and Eindhoven.
Our clients are major multinational enterprises and local companies from automotive, semiconductors, RF, consumer electronics….Our Test automation group offers a one stop shop for design of automated test benches, system integration production, lab automation and data acquisition systems, with a growing focus in IoT sensor networks.
Our consultancy department offers services in RF, semiconductors and electronics design and test, as well as on the crossing roads of Natotechnology, Bio-Sience Engeneering and Biotechnology.

Job Description

  • Take a lead and responsibility over design project(s).
  • Manage deadlines, schedule, and deliverables within the project.
  • Manage subcontractors and project consortium members.
  • Represent us in front of EU project ambassador.
  • Take a full responsibility over project results dissemination work package within electronic media.
  • Follow the company project guidelines and assure the design quality.
  • Report to stakeholders the project status and issues.

Candidate Description

  • Min 10 year of project management experience in a field of ASIC design.
  • Awareness of ASIC design flow.
  • ASIC design background.
  • Excellent presentation skills.
  • Good leadership and communication skills.
  • PM software knowledge.
  • Willing to travel by occasion.

We offer

An attractive salary package with extra benefits. A high tech, multicultural and young ambient. A fast track in a growing company. Formation in multidisciplinary environment plenty of learning opportunities.

Job Types: Full-time, Permanent contract

Schedule:

  • Monday to Friday

Experience:

  • project management experience in a field of ASIC design: 10 years (Required)
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Date limite: 31-12-2025

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