Digital Design Lead Engineer

Conteúdo do emprego

Our client is a well established and high growth Semiconductor manufacturer who are looking to grow their operations in Leuven. As a result they are looking for an experienced Digital Design lead to join their team.

Modern analog building blocks in advanced CMOS technologies need digital to improve their performance. The digitally driven self-calibrations that you will develop, and implement are a key factor to reach the target performance in today’s 5G infrastructure design.

In this role, you will be responsible for the Belgium team implementing key digital building blocks and functions to the overall digital circuit.

Responsibilities

• Leading the digital design in a cross functional team. As a principal engineer, you will guide more junior design engineers in the digital design flow and development cycle.
• Being able to setup and perform and be the key responsible for a specific pat of the digital flow from architecture, RTL, synthesis, timing analysis.
• You are organized and self-motivated, able to turn abstract ideas into concrete designs, and able to interact with the rest of the team, composed by analog designers and system engineers

Qualifications

• 10+ years of digital design experience
• Specification, design and integration of digital blocks and digital IC architecture with particular emphasis on low power design
• Block, system and chip level verification of digital and mixed signal systems
• Supporting bring-up and validation of digital systems on silicon
• Support of digital designs through the back-end flow
• Third party IP evaluation and selection
• Technical reporting both written and oral
• Strong experience in System-Verilog, Verilog, and/or VHDL
• Experience in designing signal processing, datapaths, interfaces, interconnects
• Strong knowledge of clock domain crossing (CDC) techniques, asynchronous design techniques
• Strong experience with RTL design for ASIC targets
• Strong programming and scripting skills: MATLAB, Python, C/C++, Perl, Tcl
• Experience with Design Management tools or version control tools, e.g. Git
• Good experience in EDA tools such as simulators, lint checkers (e.g. Spyglass), synthesis (e.g. Design Compiler), FPGA tools (e.g. Vivado)
• Good experience in synthesis and static timing analysis, knowledge of timing closure techniques for high-speed designs, knowledge of STA tools (e.g. PrimeTime), hardware design for asynchronous logic
• Good understanding of calibration circuits. Expertise in calibration is a plus for sure
• Good experience in hardware implementation, using tools such as Cadence, Synopsys & Xilinx
• Experience in ASIC/FPGA/SoC system-level/top-level integration
• Have good experience in DFT design

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