Senior Digital Design Engineer

☞ European Recruitment

Ver: 150

Dia de atualização: 16-11-2025

Localização: Leuven Flemish Brabant

Categoria: Alta tecnologia Produção / Operação Design - Web

Indústria: Semiconductor Manufacturing Industrial Machinery Manufacturing Computers Electronics Manufacturing

Posição: Mid-Senior level

Tipo de empregos: Full-time

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Conteúdo do emprego

Senior Digital Design Engineer / Semiconductors/ Leuven, Belgium

We are currently partnered with a leading multi-national Semiconductor company, who are looking for a Senior Digital Design Engineer to join their growing team in Leuven.

What are the key responsibilities of the Senior Digital Design Engineer?

Tthe study, design and verification of high quality ICs, technical team lead in challenging projects and the coaching of junior engineers.

What are the skills and qualifications required for the Senior Digital Design Engineer?

• At least 4 years of experience in digital IC design

• You have experience with front-end ASIC or FPGA design in VHDL and/or Verilog and/or SystemVerilog

• You have experience with front-end verification, preferably in SystemVerilog + UVM, to write directed tests, constrained randomized tests and to gather and interpret metrics such as code/condition/FSM/toggle/functional coverage

• You have experience with digital synthesis, logic equivalence checking (LEC) and Static Timing Analysis (STA) Experience with UPF and/or CPF and DFT and ATPG is a plus

• Experience with scripting and programming languages such as Python and C is a plus

• Experience with any of the following protocols and techniques is a plus: SPI, I2C, UART, CAN, LIN, SENT, DSP, CRC, FSM design, MCU

If this is of interest or you’d like some more information, please get in touch with me on:

Email: gr@eu-recruit.com

References are very welcome!

Key Words: Digital Design Engineer / IC Design / Digital Design / Analog Mixed-Signal Design / Semiconductors / Semi-conductor / Digital Design / Mixed-signal IC Design / ASIC / FPGA / VHLD / Verilog / SystemVerilog / UVM / Verification

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Data limite: 31-12-2025

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