VHDL image designer

☞ Verotech

Ver: 180

Dia de atualização: 26-11-2025

Localização: Leuven Flemish Brabant

Categoria: Mecânico / Técnico Manutenção

Indústria:

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Conteúdo do emprego

Your mission

  • Develop and maintain VHDL code for the FPGA development platform for image sensors
  • Test and verify image sensors in the lab for prototype evaluation and debugging purposes
  • Link design to evaluation, test development and customer camera integration
  • Set up and improveimage quality evaluation and analysis

Your experience

  • Master in engineering
  • 5 years of relevant experience: Hands-on lab experience
  • VHDL (FPGA) knowledge
  • RTLis a plus
  • Knowledge of Python
  • Strong communicationskills (reporting - customer interaction)

VeroTech offers you

  • Grow your talents by challenging mid to long-term R&D / Engineering projects in different industries
  • Join an inspiring community of engineers with different backgrounds and seniority levels
  • Working in a people-oriented company with an informal working environment
  • Close follow-up of your career path combined with technical and business related trainings
  • A motivating salary, with extralegal benefits and the possibility of a company car
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Data limite: 10-01-2026

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