水平: Associate

工作类型: Full-time

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工作内容

We are looking for a talented Engineer with experience and a high degree of interest in module-level, subsystem and SoC verification to support the growing verification and pre-silicon validation team targeting next-generation u-blox Cellular Communication and Positioning ASICs.

You should be committed, curious, creative, innovative, enthusiastic about new technologies, striving for excellence and willing to work in a multicultural and multi-site context. You will join a growing International team.

Key responsibilities for the successful candidate will be to own or co-own all aspects of verification and pre-silicon validation; Various areas of focus are open: Data Path, SoC, Debug, Security, etc.

Our verification team uses the latest methods including Simulation, Formal, FPGA Prototyping and Emulation.

We encourage you to apply if this role excites you – even if you think you may not meet all the requirements. We are always looking for outstanding individuals and great potentials.

Primary Tasks

  • Define Verification and Validation goals needed to make right-first-time silicon.
  • Develop Verification and Validation Plans based on specifications and team interactions (Designers, Architects, Test, Firmware, Analog) to meet targeted goals.
  • Execute the verification defined in the verification and validation plans using various methods (Simulation, Formal, FPGA Prototypes, Emulation).
  • Develop and maintain UVM environments and tests, verification components, firmware tests, firmware APIs and scripts to verify and validate module IP, Subsystems and SoCs
  • Develop, reuse and integrate C-reference models into the verification environment.
  • Analyse and investigate design behaviour to identify the root causes of failures (IP, bench, tests, flow problems).
  • Analyse verification and validation results, report, and track bugs.
  • Interact with cross-functional and cross-site teams located in multiple settings across Europe.
  • Document own work.

Profile

  • PhD, Masters or Bachelor’s Degree in Electrical, Electronics, or Computing Engineering.
  • 3+ years of industrial experience in IC design, verification and validation covering involvement in tape-outs. Relevant Academic experiences are also welcomed.
  • Experience in Cellular Communication. Positioning or similar IP, subsystems and SoCs.
  • Must have:
  • Verification oriented mindset, details-oriented and a problem-solving focus.
  • Proven experience in ASIC verification projects.
  • Prior experience in building UVM verification environment and development of System Verilog Assertions.
  • Good experience in embedded software and firmware development and associated flow for ARM based SoC (CPU/subsystem/top-level) verification
  • Firm experience, understanding and practice of Hardware description languages (VHDL, Verilog and System Verilog).
  • Preferable:
  • Experience in Functional Coverage.
  • Good understanding and practice of high-level programming languages (C/C++), Drivers, API’s and Object-Oriented Programming.
  • Lab experience in debug and investigation of Silicon and FPGA hardware.
  • Practical knowledge and experience in the development of communications ICs for 3GPP Cellular LTE and 5G.
  • Good experience in verification, validation of Integrated Circuits preferably targeting wireless communication systems (e.g. Wi-Fi, 5G, LTE, GPS/GNSS)
  • Soft skills:
  • Rigorous, Autonomous, Self-motivated, Proactive, and well organized
  • Objective driven and team-oriented
  • Good oral and written communication (English language)
  • Authorized to work in country

What are your perks?

  • Be part of a digital team with many varied and challenging tasks.
  • A multicultural and international company with over 50 different nationalities.
  • Project-based activities working with colleagues distributed across the globe.
  • A start-up and innovation mindset while in the process of scaling-up processes and efficiencies.
  • Nice location in Leuven: a vibrant city, home to the renowned KULeuven university and at the heart of Flanders DSP valley.
  • We encourage a good work life balance.
  • 29+ days of vacation a year, employee family health insurance and additional contribution from the company to the pension fund, critical illness cover, bike to work and other benefits.
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最后期限: 31-12-2025

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