Sr. Analog Design Engineer

☞ OMNIVISION

Vue: 155

Jour de mise à jour: 26-11-2025

Localisation: Mechelen Antwerp

Catégorie: Haute technologie IT - Logiciel

Industrie: Semiconductor Manufacturing

Niveau: Mid-Senior level

Type d’emploi: Full-time

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le contenu du travail

DescriptionCover letter outlining your motivation to move to , live and work in Belgium , along with a description of what makes you interested and suited for the role is required with submittal of your CVThe Sr. Analog Design Engineer will be joining our team to develop the next generation of image sensors. In a rapidly developing industry, we are looking for talent to help drive our innovation and continuous improvements to be technology leaders in the industry. You will design circuits for pixel array readout, amplifiers, ADCs, low noise regulators, and other components for use in our state of the art image sensors. You’re expected to take up technical leadership and support less experienced engineers.Responsibilities
  • Specify and implement analog and mixed signal sub-blocks based on project objectives.
  • Implement blocks on transistor and layout level and perform physical verification using CAD tools such as Cadence, Synopsys and Mentor Graphics.
  • Verify by simulation, sub-blocks and chip top level from a system perspective, including IR drop on power supplies and cross-talk effects.
  • Debug, characterize and optimize performance for fabricated sensor chips.
  • Contribute to circuit innovation and continuous improvement of design methodology.
  • Mentor/guide/support less experienced engineers when necessary.
  • Support and/or be the Technical Project Lead on our projects.
Qualifications
  • Minimum MSEE in electrical engineering with at least 5 yrs. of experience in analog design.
  • Excellent command of English as a working language.
  • Experience in image sensor design is a plus.
  • Experience in technical leadership of projects or IP-blocks is a plus.
  • Lab experience is a plus.
  • Knowledge of Mentor Calibre is a plus.
  • Knowledge of Cadence Virtuoso is a plus.
  • Knowledge of Python is a plus.
  • Knowledge of behavioral modeling in Verilog, System Verilog, Verilog-A, Verilog-AMS is a plus.
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Date limite: 10-01-2026

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